High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention
Abstract This article presents a serializer (SER) timing‐error detection circuit that enhances the verification reliability of high‐speed wireline interfaces. A timing mismatch in the SER leads to bit errors during data transmission. To detect the timing error, the proposed design employs a set‐rese...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2024-12-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.70121 |
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