High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention
Abstract This article presents a serializer (SER) timing‐error detection circuit that enhances the verification reliability of high‐speed wireline interfaces. A timing mismatch in the SER leads to bit errors during data transmission. To detect the timing error, the proposed design employs a set‐rese...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Wiley
2024-12-01
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| Series: | Electronics Letters |
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| Online Access: | https://doi.org/10.1049/ell2.70121 |
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| _version_ | 1850105104856776704 |
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| author | Jongchan Lee Joo‐Hyung Chae |
| author_facet | Jongchan Lee Joo‐Hyung Chae |
| author_sort | Jongchan Lee |
| collection | DOAJ |
| description | Abstract This article presents a serializer (SER) timing‐error detection circuit that enhances the verification reliability of high‐speed wireline interfaces. A timing mismatch in the SER leads to bit errors during data transmission. To detect the timing error, the proposed design employs a set‐reset latch to self‐latch the detection result, improving the error detection accuracy, unlike the previously reported timing‐error detection design using a D flip‐flop. The prototype transmitter chip, fabricated using a 28‐nm CMOS process, was validated for accurate error detection across wide data rates ranging from 1.25 to 13 Gb/s, ensuring reliable high‐speed operation while efficiently handling timing mismatches across multiple SER stages. |
| format | Article |
| id | doaj-art-025aa532e8794a14b1fe333129ceca24 |
| institution | DOAJ |
| issn | 0013-5194 1350-911X |
| language | English |
| publishDate | 2024-12-01 |
| publisher | Wiley |
| record_format | Article |
| series | Electronics Letters |
| spelling | doaj-art-025aa532e8794a14b1fe333129ceca242025-08-20T02:39:11ZengWileyElectronics Letters0013-51941350-911X2024-12-016024n/an/a10.1049/ell2.70121High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state preventionJongchan Lee0Joo‐Hyung Chae1Department of Electronics and Communications Engineering Kwangwoon University Seoul South KoreaDepartment of Electronics and Communications Engineering Kwangwoon University Seoul South KoreaAbstract This article presents a serializer (SER) timing‐error detection circuit that enhances the verification reliability of high‐speed wireline interfaces. A timing mismatch in the SER leads to bit errors during data transmission. To detect the timing error, the proposed design employs a set‐reset latch to self‐latch the detection result, improving the error detection accuracy, unlike the previously reported timing‐error detection design using a D flip‐flop. The prototype transmitter chip, fabricated using a 28‐nm CMOS process, was validated for accurate error detection across wide data rates ranging from 1.25 to 13 Gb/s, ensuring reliable high‐speed operation while efficiently handling timing mismatches across multiple SER stages.https://doi.org/10.1049/ell2.70121error detectionhigh‐speed integrated circuitstransmitters |
| spellingShingle | Jongchan Lee Joo‐Hyung Chae High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention Electronics Letters error detection high‐speed integrated circuits transmitters |
| title | High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention |
| title_full | High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention |
| title_fullStr | High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention |
| title_full_unstemmed | High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention |
| title_short | High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention |
| title_sort | high speed serializer timing error detection circuit with enhanced verification reliability through floating state prevention |
| topic | error detection high‐speed integrated circuits transmitters |
| url | https://doi.org/10.1049/ell2.70121 |
| work_keys_str_mv | AT jongchanlee highspeedserializertimingerrordetectioncircuitwithenhancedverificationreliabilitythroughfloatingstateprevention AT joohyungchae highspeedserializertimingerrordetectioncircuitwithenhancedverificationreliabilitythroughfloatingstateprevention |