On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors
Reconfigurable instruction set processors provide the possibility of tailor the instruction set of a CPU to a particular application. While this customization process could be performed during runtime in order to adapt the CPU to the currently executed workload, this use case has been hardly investi...
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/418315 |
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| _version_ | 1832554472215150592 |
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| author | Mariusz Grad Christian Plessl |
| author_facet | Mariusz Grad Christian Plessl |
| author_sort | Mariusz Grad |
| collection | DOAJ |
| description | Reconfigurable instruction set processors provide the possibility of tailor the instruction set of a CPU to a particular application. While this customization process could be performed during runtime in order to adapt the CPU to the currently executed workload, this use case has been hardly investigated. In this paper, we study the feasibility of moving the customization process to runtime and evaluate the relation of the expected speedups and the associated overheads. To this end, we present a tool flow that is tailored to the requirements of this just-in-time ASIP specialization scenario. We evaluate our methods by targeting our previously introduced Woolcano reconfigurable ASIP architecture for a set of applications from the SPEC2006, SPEC2000, MiBench, and SciMark2 benchmark suites. Our results show that just-in-time ASIP specialization is promising for embedded computing applications, where average speedups of 5x can be achieved by spending 50 minutes for custom instruction identification and hardware generation. These overheads will be compensated if the applications execute for more than 2 hours. For the scientific computing benchmarks, the achievable speedup is only 1.2x, which requires significant execution times in the order of days to amortize the overheads. |
| format | Article |
| id | doaj-art-01577768fc234d85bd85e93d0b8ccb4d |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-01577768fc234d85bd85e93d0b8ccb4d2025-02-03T05:51:22ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092012-01-01201210.1155/2012/418315418315On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable ProcessorsMariusz Grad0Christian Plessl1Paderborn Center for Parallel Computing, University of Paderborn, 33098 Paderborn, GermanyPaderborn Center for Parallel Computing, University of Paderborn, 33098 Paderborn, GermanyReconfigurable instruction set processors provide the possibility of tailor the instruction set of a CPU to a particular application. While this customization process could be performed during runtime in order to adapt the CPU to the currently executed workload, this use case has been hardly investigated. In this paper, we study the feasibility of moving the customization process to runtime and evaluate the relation of the expected speedups and the associated overheads. To this end, we present a tool flow that is tailored to the requirements of this just-in-time ASIP specialization scenario. We evaluate our methods by targeting our previously introduced Woolcano reconfigurable ASIP architecture for a set of applications from the SPEC2006, SPEC2000, MiBench, and SciMark2 benchmark suites. Our results show that just-in-time ASIP specialization is promising for embedded computing applications, where average speedups of 5x can be achieved by spending 50 minutes for custom instruction identification and hardware generation. These overheads will be compensated if the applications execute for more than 2 hours. For the scientific computing benchmarks, the achievable speedup is only 1.2x, which requires significant execution times in the order of days to amortize the overheads.http://dx.doi.org/10.1155/2012/418315 |
| spellingShingle | Mariusz Grad Christian Plessl On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors International Journal of Reconfigurable Computing |
| title | On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors |
| title_full | On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors |
| title_fullStr | On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors |
| title_full_unstemmed | On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors |
| title_short | On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors |
| title_sort | on the feasibility and limitations of just in time instruction set extension for fpga based reconfigurable processors |
| url | http://dx.doi.org/10.1155/2012/418315 |
| work_keys_str_mv | AT mariuszgrad onthefeasibilityandlimitationsofjustintimeinstructionsetextensionforfpgabasedreconfigurableprocessors AT christianplessl onthefeasibilityandlimitationsofjustintimeinstructionsetextensionforfpgabasedreconfigurableprocessors |