Improving MRAM Performance with Sparse Modulation and Hamming Error Correction

With the rise of the Internet of Things (IoT), smart sensors are increasingly being deployed as compact edge processing units, necessitating continuously writable memory with low power consumption and fast access times. Magnetic random-access memory (MRAM) has emerged as a promising non-volatile alt...

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Main Authors: Nam Le, Thien An Nguyen, Jong-Ho Lee, Jaejin Lee
Format: Article
Language:English
Published: MDPI AG 2025-06-01
Series:Sensors
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Online Access:https://www.mdpi.com/1424-8220/25/13/4050
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author Nam Le
Thien An Nguyen
Jong-Ho Lee
Jaejin Lee
author_facet Nam Le
Thien An Nguyen
Jong-Ho Lee
Jaejin Lee
author_sort Nam Le
collection DOAJ
description With the rise of the Internet of Things (IoT), smart sensors are increasingly being deployed as compact edge processing units, necessitating continuously writable memory with low power consumption and fast access times. Magnetic random-access memory (MRAM) has emerged as a promising non-volatile alternative to conventional DRAM and SDRAM, offering advantages such as faster access speeds, reduced power consumption, and enhanced endurance. However, MRAM is subject to challenges including process variations and thermal fluctuations, which can induce random bit errors and result in imbalanced probabilities of 0 and 1 bits. To address these issues, we propose a novel sparse coding scheme characterized by a minimum Hamming distance of three. During the encoding process, three check bits are appended to the user data and processed using a generator matrix. If the resulting codeword fails to satisfy the sparsity constraint, it is inverted to comply with the coding requirement. This method is based on the error characteristics inherent in MRAM to facilitate effective error correction. Furthermore, we introduce a dynamic threshold detection technique that updates bit probability estimates in real time during data transmission. Simulation results demonstrate substantial improvements in both error resilience and decoding accuracy, particularly as MRAM density increases.
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spelling doaj-art-00f8272ec25c467fb9ffc97c6d27b56e2025-08-20T03:29:02ZengMDPI AGSensors1424-82202025-06-012513405010.3390/s25134050Improving MRAM Performance with Sparse Modulation and Hamming Error CorrectionNam Le0Thien An Nguyen1Jong-Ho Lee2Jaejin Lee3Department of Information Communication Convergence Technology, Soongsil University, Seoul 06978, Republic of KoreaDepartment of Information Communication Convergence Technology, Soongsil University, Seoul 06978, Republic of KoreaSchool of Electronic Engineering, Soongsil University, Seoul 06978, Republic of KoreaDepartment of Information Communication Convergence Technology, Soongsil University, Seoul 06978, Republic of KoreaWith the rise of the Internet of Things (IoT), smart sensors are increasingly being deployed as compact edge processing units, necessitating continuously writable memory with low power consumption and fast access times. Magnetic random-access memory (MRAM) has emerged as a promising non-volatile alternative to conventional DRAM and SDRAM, offering advantages such as faster access speeds, reduced power consumption, and enhanced endurance. However, MRAM is subject to challenges including process variations and thermal fluctuations, which can induce random bit errors and result in imbalanced probabilities of 0 and 1 bits. To address these issues, we propose a novel sparse coding scheme characterized by a minimum Hamming distance of three. During the encoding process, three check bits are appended to the user data and processed using a generator matrix. If the resulting codeword fails to satisfy the sparsity constraint, it is inverted to comply with the coding requirement. This method is based on the error characteristics inherent in MRAM to facilitate effective error correction. Furthermore, we introduce a dynamic threshold detection technique that updates bit probability estimates in real time during data transmission. Simulation results demonstrate substantial improvements in both error resilience and decoding accuracy, particularly as MRAM density increases.https://www.mdpi.com/1424-8220/25/13/4050asymmetric write error ratecascaded channelerror correction codes (ECCs)the Hamming codenon-volatile RAMsparse codes
spellingShingle Nam Le
Thien An Nguyen
Jong-Ho Lee
Jaejin Lee
Improving MRAM Performance with Sparse Modulation and Hamming Error Correction
Sensors
asymmetric write error rate
cascaded channel
error correction codes (ECCs)
the Hamming code
non-volatile RAM
sparse codes
title Improving MRAM Performance with Sparse Modulation and Hamming Error Correction
title_full Improving MRAM Performance with Sparse Modulation and Hamming Error Correction
title_fullStr Improving MRAM Performance with Sparse Modulation and Hamming Error Correction
title_full_unstemmed Improving MRAM Performance with Sparse Modulation and Hamming Error Correction
title_short Improving MRAM Performance with Sparse Modulation and Hamming Error Correction
title_sort improving mram performance with sparse modulation and hamming error correction
topic asymmetric write error rate
cascaded channel
error correction codes (ECCs)
the Hamming code
non-volatile RAM
sparse codes
url https://www.mdpi.com/1424-8220/25/13/4050
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