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    Speeding Up FPGA Placement via Partitioning and Multithreading

    Speeding Up FPGA Placement via Partitioning and Multithreading by Cristinel Ababei

    Published 2009-01-01
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  2. 2
    3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans

    3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans by Vitor de Paulo, Cristinel Ababei

    Published 2010-01-01
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