Scalable Low Power Accelerator for Sparse Recurrent Neural Network - Panshi JIN; Junjie LI; Jingyi WANG; Pengchong LI; Lei XING; Xiaodong LI (天地一体化信息网络)
The use of edge computing devices in bank outlets for passenger flow analysis, security protection, risk prevention and control is increasingly widespread, among which the performance and power consumption of AI reasoning chips have become a very important factor in the selection of edge computing devices.Aiming at the problems of recurrent neural network, such as high power consumption, weak reasoning performance and low energy efficiency, which were caused by data dependence and low data reusability, this paper realized a sparse RNN low-power accelerator with scalable voltage by using FPGA, and verifies it on the edge design and calculation equipment.Firstly, the sparse -RNN was analyzed and the processing array was designed by network compression.Secondly, due to the unbalanced workload of sparse RNN, it introduced voltage scaling method to maintain low power consumption and high throughput.Experiments show that this method could significantly improve the RNN reasoning speed of the system and reduce the processing power consumption of the chip.