Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime - Asisa Kumar Panigrahy; Sudheer Hanumanthakari; Shridhar B. Devamane; Shruti Bhargava Choubey; M. Prasad; D. Somasundaram; N. Kumareshan; N. Arun Vignesh; Gnanasaravanan Subramaniam; Durga Prakash M; Raghunandan Swain (IEEE Open Journal of Nanotechnology)
This research focuses on a quantum model created using an entirely novel nanosheet FET. The standard model describes the performance of a Gate-all-around (GAA) Junction-less (JL) nanosheet device with a gate dielectric of SiO2 and HfO2, each having a thickness of 1 nm. The performance of both the classical and quantum models of the GAA nanosheet device is evaluated using the visual TCAD tool, which measures the ION, IOFF, ION/ IOFF, threshold voltage, DIBL, gain parameters (gm, gd, Av), gate capacitance, and cut-off frequency (fT). The device is suited for applications needing rapid switching since it has a low gate capacitance of the order of 10–18, according to the simulation results. A transconductance (gm) value of 21 µS and an impressive cut-off frequency of 9.03 GHz are displayed during device analysis. A detailed investigation has also been done into the P-type device response for the same device. Finally, the proposed GAA nanosheet device is used in the inverter model. The NSFET-based inverter, although having higher gate capacitance, has the shortest propagation latency.