A low time mismatch sampling method for time-interleaved ADC - Yan Xiang; Qin Kefan; Yang Shangzheng; Hu Weibo (Dianzi Jishu Yingyong)
To cope with the performance degradation caused by time mismatch in time-interleaved analog-to-digital converters, an efficient hierarchical series sampling method was proposed. The idea of this sampling method is to aggregate the clock sources related to sampling accuracy at the main sampling switch position, to alleviate the sampling accuracy degradation due to time mismatch in the control clock of multiple sub-sampling switches. In addition, a high-speed bootstrap sampling switch is also designed, which has the characteristics of fast opening speed and high linearity. The sampling method is based on the 22 nm CMOS process to build the circuit and carry out post-simulation verification. The post-layout simulation results show that the sampling method is not sensitive to time mismatch, and the signal noise distortion ratio (SNDR) of the sampling network reaches 72 dB at a supply voltage of 0.9 V and an input signal frequency of 2 GHz.