A Comprehensive Study of Threshold Voltage Extraction Techniques From Room to Cryogenic Temperatures - Wajid Manzoor; Aloke K. Dutta; Yogesh Singh Chauhan (IEEE Journal of the Electron Devices Society)
In this article, we present a comprehensive overview of the negative transconductance observed in native (or zero-threshold) MOSFETs at cryogenic temperatures. These devices exhibit negative transconductance, characterized by a drop in the drain-to-source current as the gate voltage increases below 77 K, a behavior observed in earlier works. The parameters related to mobility and threshold voltage exert an influence on the negative transconductance. Based on an in-depth analysis of these parameters on the characteristics of zero-threshold voltage devices, we present a modeling methodology that effectively incorporates the negative transconductance effect using BSIM-Bulk as the core model. The model results are validated with the experimental data, demonstrating an excellent match between the two. After validating our model, we used the data from the native device to extract the threshold voltage at various temperatures using different methods. It has been observed that the increase in the threshold voltage is nonlinear with respect to a decrease in temperature. In order to explain this trend, we used the surface potential, drain current, and transconductance to calculate the threshold voltage at different temperatures. The surface potential method is the basic method and gives an idea about the changes observed in the electrostatics of the device at various temperatures. However, in actual devices, transport factors also play a crucial role. Therefore, we have used drain current, transconductance, and the ratio of these to extract the threshold voltage at various temperatures. The comparison and corresponding advantages and disadvantages of each of these methods are also discussed.