A Fully Integrated Memristive Chaotic Circuit Based on Memristor Emulator with Voltage-Controlled Oscillator - Zhikui Duan; Jiahui Chen; Shaobo He; Xinmei Yu; Qiang Wang; Xin Zhang; Peng Xiong (Micromachines)
This paper introduces a fully integrated memristive chaotic circuit, which is based on a voltage-controlled oscillator (VCO). The circuit employs a fully integrated architecture that offers reduced power consumption and a smaller footprint compared to the use of discrete components. Specifically, the VCO is utilized to generate the oscillatory signal, whereas the memristor emulator circuit serves as the nonlinear element. The memristor emulator circuit is constructed using a single operational transconductance amplifier (OTA), two transistors, and a grounded capacitor. This straightforward design contributes to diminished power usage within the chip’s area. The VCO incorporates a dual delay unit and implements current compensation to enhance the oscillation frequency and to broaden the VCO’s tunable range. Fabricated using the SMIC 180 nm CMOS process, this chaotic circuit occupies a mere 0.0072 mm2 of chip area, demonstrating a design that is both efficient and compact. Simulation outcomes indicate that the proposed memristor emulator is capable of operating at a maximum frequency of 300 MHz. The memristive chaotic circuit is able to produce a chaotic oscillatory signal with an operational frequency ranging from 158 MHz to 286 MHz, powered by a supply of 0.9 V, and with a peak power consumption of 3.5553 mW. The Lyapunov exponent of the time series within the resultant chaotic signal spans from 0.2572 to 0.4341.