Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effect - LI Can; LIU Yunhua; LIU Guowang; WU Jian; WANG Fuguang; ZHANG Yi (机车电传动)
The reliability of input inrush current suppression circuits is crucial for ensuring the stable operation of power boards, deemed one of the fundamental requirements for the safe operation of electric locomotives. In order to improve this reliability, this paper proposed a series of optimization measures based on the failure instance involving anti-inrush metal oxide semiconductor field effect transistors (MOSFET) in a power supply application. The initial analysis addressed the waveform timing of MOSFETs using a simplified model, deriving the working principles and related calculation formulas for input inrush current suppression circuits. Subsequently, a loss evaluation method for the MOSFETs’ safe operation area (SOA) was introduced, based on the Miller effect. Through evaluating SOA loss in the measured waveform, the root cause of the anti-inrush MOSFET failure was identified to be the insufficient power derating of the device at elevated temperatures. To address this issue, optimization measures were proposed, such as adjusting the device model according to failure cause, extending the Miller platform time, and implementing a delayed start-up. The results from model simulations were harnessed to calculate energy demands for switching on the anti-inrush MOSFET and energy bearing limits under various input conditions. The calculation results show that the MOSFET power derating after optimization aligned with requirements throughout the entire input voltage and temperature ranges. The subsequent experiments were conducted on an engineering prototype under full conditions. The experimental results demonstrated the efficacy of the proposed optimization measures in effectively enhancing the reliability of input inrush current suppression circuits.